Soft error rates in caches are increasing due to several factors, among them increasing cache sizes and increased “erratic bit” behavior in manufacturing processes. For this reason, some processors may utilize DECTED (Double-bit Error Correction, Triple-bit Error Detection) ECC (Error Correction Code) protection for the LLC (Last Level Cache).
One disadvantage of DECTED is that detection and correction are more expensive than SECDED (Single-bit Error Correction, Double-bit Error Detection) in terms of area, power, and/or latency. Also, as LLC hit latency may be critical to application performance, more efficient error correction may directly improve processor performance.